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 IC62VV1008L IC62VV1008LL
Document Title
1 M x 8 bit Low Voltage and Ultra Low Power CMOS Static RAM
Revision History
Revision No
0A
History
Initial Draft
Draft Date
September 4,2002
Remark
Preliminary
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
LPSR026-0A 9/4/2002
1
IC62VV1008L IC62VV1008LL
1M x 8 1.8V ULTRA LOW POWER CMOS STATIC RAM
FEATURES
* Access times of 70, 100 ns * CMOS Low power operation: ICC=10mA (typical)* operation ISB2=3A (typical)* standby * Low data retention voltage: 1.2V (min.) * Output Enable (OE) and Two Chip Enables (CE1, CE2) inputs for ease in applications * TTL compatible inputs and outputs * Fully static operation: -- No clock or refresh reguired * Single 1.65V-2.2V power supply * Wafer level burn in test mode * Available in the know good die form and 48-pin 8*10mm TF-BGA
* Typical values are measured at VCC=1.8V, TA=25C
Preliminary
DESCRIPTION The ICSI IC62VV1008L and IC62VV1008LL is a low voltage,
1,048,576 words by 8 bits, CMOS SRAM. It is fabricated using ICSI's low voltage, six transistor (6T), CMOS technology. The device is targeted to satisfy the demands of the state-of-the-art technologies such as cell phones and pagers. When CE1 is HIGH or CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Additionally, easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable ( WE) controls both writing and reading of the memory. The IC62VV1008L and IC62VV1008LL are available in know good die form and 48-pin 8*10mm TF-BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A19
DECODER
1024K x 8 MEMORY ARRAY
VCC GND I/O DATA CIRCUIT
I/O0-I/O7
COLUMN I/O
CE1 CE2 OE WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc.
CONTROL CIRCUIT
2
Integrated Circuit Solution Inc.
LPSR026-0A 9/4/2002
IC62VV1008L IC62VV1008LL
PIN CONFIGURATIONS
48-Pin 8*10mm TF-BGA (TOP View)
1 A B C D E F G H
NC NC I/O0 GND Vcc I/O3 NC A18
2
OE NC NC I/O1 I/O2 NC NC A8
3
A0 A3 A5 A17 Vcc A14 A12 A9
4
A1 A4 A6 A7 A16 A15 A13 A10
5
A2 CE1 NC I/O5 I/O6 NC WE A11
6
CE2 NC I/O4 Vcc GND I/O7 NC A19
PIN DESCRIPTIONS
A0-A19 CE1 CE2 OE WE I/O0-I/O7 NC Vcc GND Address Inputs Chip Enable 1 Input Chip Enable 2 Input Output Enable Input Write Enable Input Data Input/Output No Connection Power Ground
TRUTH TABLE
Mode Not Selected (POWER-DOWN) Output Disabled Read Write WE X X H H L CE1 H X L L L CE2 X L H H H OE X X H L X I/O Operation High-Z High-Z High-Z DOUT DIN Vcc Current ISB2 ISB2 ICC ICC ICC
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 1.65V - 2.2V 1.65V - 2.2V
Integrated Circuit Solution Inc.
LPSR026-0A 9/4/2002
3
IC62VV1008L IC62VV1008LL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM VCC TBIAS TSTG PT Parameter Terminal Voltage with Respect to GND Vcc related to GND Temperature Under Bias Storage Temperature Power Dissipation Value -0.5 to Vcc +0.4 -0.3 to +2.4 -40 to +85 -65 to +150 1 Unit V V C C W
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE(1)(2)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25oC, f = 1 MHz, VCC = 3.0 V
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage(1) Input LOW Voltage(2) Input Leakage Output Leakage Test Conditions VCC = Min., IOH = -0.1 mA VCC = Min., IOL = 0.1 mA Min. 1.4 -- 1.4 -0.2 -1 -1 Max. -- 0.2 VCC + 0.2 0.4 1 1 Unit V V V V A A
GND VIN VCC GND VOUT VCC
Notes: 1. VIH(max.) = VCC +2.0V for pulse width less than 10 ns. 1. VIL(min.) = -2.0V for pulse width less than 10 ns.
4
Integrated Circuit Solution Inc.
LPSR026-0A 9/4/2002
IC62VV1008L IC62VV1008LL
IC62VV1008L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-70 Symbol Parameter ICC1 ICC2 Vcc Dynamic Operating Supply Current Vcc Dynamic Operating Supply Current CMOS Standby Current (CMOS Inputs) Test Conditions VCC = 1.8V, CE1 = VIL,CE2=VIH IOUT = 0 mA, f = fMAX VCC = 1.8V CE1 = VIL, CE2 = VIH, IOUT = 0 mA, f = 1MHZ VCC = Max., f = 0 CE1 VCC - 0.2V or CE2 0.2V, VIN VCC - 0.2V, VIN 0.2V Com. Ind. Com. Ind. Com. Ind. Min. -- -- -- -- -- -- -100 Max. Min. Max. 15 20 -- -- 12 15 2.5 2.5 35 50 Unit mA mA
2.5 -- 2.5 -- 35 50 -- --
ISB2
A
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IC62VV1008LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-70 Symbol Parameter ICC1 ICC2 VCC Dynamic Operating Supply Current VCC Dynamic Operating Supply Current CMOS Standby Current (CMOS Inputs) Test Conditions VCC = 1.8V, CE1 = VIL, CE2=VIH IOUT = 0 mA, f = fMAX VCC = 1.8V CE1 = VIL, CE2=VIH f = 1MHZ VCC = Max., f = 0 CE1 VCC - 0.2V or CE2 0.2V, VIN VCC - 0.2V, VIN 0.2V Com. Ind. Com. Ind. Com. Ind. Min. -- -- -- -- -- -- Max. Min. 15 20 -- -- -100 Max. Unit 12 15 2.5 2.5 15 25 mA mA
2.5 -- 2.5 -- 15 25 -- --
ISB2
A
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Circuit Solution Inc.
LPSR026-0A 9/4/2002
5
IC62VV1008L IC62VV1008LL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-70 Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE1 Access Time CE2 Access Time OE Access Time Min. 70 -- 10 -- -- -- 5 0 10 10 0 Max. -- 70 -- 70 70 35 -- 25 -- -- 25 -100 Min. Max. 100 -- 15 -- -- -- 5 0 10 10 0 -- 100 -- 100 100 50 -- 30 -- -- 30 Unit ns ns ns ns ns ns ns ns ns ns ns
tRC tAA tOHA tACE1 tACE2 tDOE
tLZOE(2) OE to Low-Z Output tHZOE(2) OE to High-Z Output tLZCE1 tLZCE2
(2) (2)
CE1 to Low-Z Output CE2 to Low-Z Output
tHZCE(2) CE1 or CE2 to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 1.4V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input Reference Level Output Reference Level Output Load Unit 0.4V to 1.4V 5 ns 0.9V 0.9V See Figures 1 and 2
AC TEST LOADS
1 TTL OUTPUT 100 pF Including jig and scope
OUTPUT 5 pF Including jig and scope 1 TTL
Figure 1
Figure 2
6
Integrated Circuit Solution Inc.
LPSR026-0A 9/4/2002
IC62VV1008L IC62VV1008LL
AC TEST LOADS READ CYCLE NO.1(1,2) (Address controlled, CE1 = OE = VIL , CE2 = VIH)
t RC
ADDRESS
t AA t OHA
DOUT
PREVIOUS DATA VALID
t OHA
DATA VALID
AC WAVEFORMS READ CYCLE NO. 2(1,3) (CE1, OE CE2 controlled) OE,
tRC
ADDRESS
tAA tOHA
OE
tDOE tHZOE
CE1
tACE1/tACE2
tLZOE
CE2
tLZCE1/ tLZCE2
HIGH-Z
tHZCE
DATA VALID
DOUT
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
Integrated Circuit Solution Inc.
LPSR026-0A 9/4/2002
7
IC62VV1008L IC62VV1008LL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low Power)
Symbol Parameter Write Cycle Time CE1 to Write End CE2 to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time
(4)
Min. 55 50 50 50 0 0 45 25 0 -- 5
-55 Max. -- -- -- -- -- -- -- -- -- 30 --
Min. 70 65 65 65 0 0 55 30 0 -- 5
-70 Max. -- -- -- -- -- -- -- -- -- 30 --
-100 Min. Max 100 80 80 80 0 0 80 40 0 -- 5 -- -- -- -- -- -- -- -- -- 40 --
Unit ns ns ns ns ns ns ns ns ns ns ns
tWC tSCE1 tSCE2 tAW tHA tSA tPWE tSD tHD tHZWE tLZWE
(3) (3)
WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 5 ns or less, input pulse levels of 0.4V to 1.4V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1 LOW , CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH.
AC WAVEFORMS WRITE CYCLE NO. 1
(WE Controlled) (1,2)
tWC
ADDRESS
tSCE1 tHA
CE1
tSCE2
CE2
tAW tPWE tSA tHZWE
HIGH-Z
WE
tLZWE
DOUT
DATA UNDEFINED
tSD
tHD
DIN
DATA-IN VALID
8
Integrated Circuit Solution Inc.
LPSR026-0A 9/4/2002
IC62VV1008L IC62VV1008LL
WRITE CYCLE NO. 2
(CE1, CE2 Controlled)(1,2)
tWC
ADDRESS
tSA tSCE1 tHA
CE1
tSCE2
CE2
tAW tPWE
WE
tHZWE tLZWE
HIGH-Z
DOUT
DATA UNDEFINED
tSD
tHD
DIN
DATA-IN VALID
Notes: 1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the HIGH-z state if OE =VIH.
Integrated Circuit Solution Inc.
LPSR026-0A 9/4/2002
9
IC62VV1008L IC62VV1008LL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Vcc for Data Retention Data Retention Current Test Condition See Data Retention Waveform Vcc = 1.2V, CE1 Vcc - 0.2V Com. (-L) Com. (-LL) Ind. (-L) Ind. (-LL) Min. 1.2 -- -- -- -- 0 Max. 2.2 20 13 30 23 -- -- Unit V A A A A ns ns
VDR
IDR
tSDR tRDR
Data Retention Setup Time Recovery Time
See Data Retention Waveform See Data Retention Waveform
10
DATA RETENTION WAVEFORM (CE1 Controlled)
tSDR VCC 1.65V Data Retention Mode tRDR
1.4V
VDR CE1 VCC - 0.2V
CE1 GND
10
Integrated Circuit Solution Inc.
LPSR026-0A 9/4/2002
IC62VV1008L IC62VV1008LL
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) Order Part No. 70 100 IC62VV1008L-70B IC62VV1008L-100B Package 8*10mm TF-BGA 8*10mm TF-BGA
Industrial Range: -40C to +85C
Speed (ns) Order Part No. 70 100 IC62VV1008L-70BI IC62VV1008L-100BI Package 8*10mm TF-BGA 8*10mm TF-BGA
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) Order Part No. 70 100 IC62VV1008LL-70B IC62VV1008LL-70D Package 8*10mm TF-BGA know good die
Industrial Range: -40C to +85C
Speed (ns) Order Part No. 70 100 IC62VV1008LL-70BI IC62VV1008LL-70DI Package 8*10mm TF-BGA know good die
IC62VV1008LL-100B 8*10mm TF-BGA IC62VV1008LL-100D know good die
IC62VV1008LL-100BI 8*10mm TF-BGA IC62VV1008LL-100DI know good die
Integrated Circuit Solution Inc.
HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw
Integrated Circuit Solution Inc.
LPSR026-0A 9/4/2002
11


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